The PCIE Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The PCIE Controller IIP can be implemented in any technology.

The PCIE Controller IIP core supports the PCI 5.0 Specification. It can also support a variety of host bus interfaces for easy adoption into any design architecture – AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone  or  custom buses.

The PCIE Controller IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The PCIE Controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.