The DMA Controller with TileLink interface is full featured, easy-to-use, synthesizable design that can be used with TileLink based systems as a controller to transfer data directly from system memory to IP core or from IP core to system memory.

The DMA Controller TileLink IIP core supports TileLink 1.7.1 specification. Through its compatibility, it provides a simple interface to any IP core with the appropriate logic in between. The DMA Controller TileLink IIP can be implemented in any technology.

The DMA Controller TileLink IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The DMA Controller TileLink IIP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.