The DDR4 Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The DDR4 Controller IIP can be implemented in any technology.

The DDR4 Controller IIP core supports the DDR4 protocol standard of JESD79-4,JESD79-4A, JESD79-4A_r2, JESD79-4B, JESD79-4C and JESD79-4D (Draft) specifications and is compatible with DFI-version 3.0 or higher Specification Compliant.DDR4 Controller IIP also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

The DDR4 Controller IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The DDR4 Controller IIP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.