The eCPRI Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The eCPRI Controller IIP can be implemented in any technology.

The eCPRI Controller IIP core is compliant with eCPRI Specification v2.1 It can also support a variety of host bus interfaces for easy adoption into any design architecture – AHB,AHB-Lite, APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or custom buses.

The eCPRI Controller IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The eCPRI Controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.